Back

perf: RISC-V: store available counter mask as bitmap

Published Sep 25, 2026

Description

The available-counter mask was a single unsigned long, but iteration uses RISCV_MAX_COUNTERS, which is 64. On RV32 that reads past the object. Filling with an unsigned-long bit at index 32 and above is also wrong.

Use DECLARE_BITMAP and set_bit/bitmap helpers. Walk each bitmap word into CFG_MATCH when checking events, when allocating an index, and when stopping all counters. Set the counter base to i times BITS_PER_LONG. Share the CFG_MATCH ecall through a small helper so the 32-bit argument split is not duplicated. On qemu-system-riscv32 the probe bitmap has bits above XLEN set, so the first word alone is not enough.

[pjw@kernel.org: updated to apply; fixed checkpatch.pl issues]

Affected products

Remediation

No remediation recorded yet.

Weaknesses (0)

No CWE recorded.

References (5)

Change history (0)

No recorded changes yet.

Sources

CVE.org / MITRE

Status PUBLISHED
Assigner Linux
Published Sep 25, 2026
Updated Sep 25, 2026
Reserved Sep 24, 2026

CISA Vulnrichment

No data

NVD

Status Received
Modified Sep 25, 2026

Red Hat

No data

ENISA EUVD

Assigner Linux
Published Sep 25, 2026
Updated Sep 25, 2026

GitHub

No data