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pmdomain: imx8m-blk-ctrl: Remove separate rst and clk mask for 8mq vpu

Published Feb 14, 2026

Description

For i.MX8MQ platform, the ADB in the VPUMIX domain has no separate reset and clock enable bits, but is ungated and reset together with the VPUs. So we can't reset G1 or G2 separately, it may led to the system hang. Remove rst_mask and clk_mask of imx8mq_vpu_blk_ctl_domain_data. Let imx8mq_vpu_power_notifier() do really vpu reset.

Affected products

Remediation

Red Hat statement

On i.MX8MQ the VPUMIX domain ADB block does not provide separate reset and clock enable bits per VPU instance. The previous power domain data defined per domain rst_mask and clk_mask values for vpublk g1 and vpublk g2. As a result the kernel could attempt to reset or ungate one VPU independently. That hardware sequence is invalid on i.MX8MQ and can lead to a full system hang. This is an availability issue that can be triggered by local activity that causes VPU power management transitions. Such activity can be reached through driver probe and remove. Runtime PM operations. Or higher level multimedia usage that toggles VPU domains. The patch removes the per domain rst_mask and clk_mask so the generic block control code will not try to reset or clock gate G1 or G2 separately. Instead the existing imx8mq_vpu_power_notifier is relied on to perform the correct combined VPU reset sequence. The main impact is preventing a local denial of service on affected embedded systems.

Weaknesses (1)

References (11)

Change history (0)

No recorded changes yet.

Sources
CVE.org / MITRE
Status PUBLISHED
Assigner Linux
Published Feb 14, 2026
Updated May 11, 2026
Reserved Jan 13, 2026
NVD
Status Analyzed
Modified Jun 17, 2026
Red Hat
Severity Moderate
Public date Feb 14, 2026
ENISA EUVD
Assigner Linux
Published Feb 14, 2026
Updated May 11, 2026
Exploited since n/a
EUVD-2026-6030