CVE-2020-0574 - Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access

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MEDIUM

Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access

Published Mar 12, 2020

5.9

MEDIUM

CVSS 3.1

EPSS 0.36%

Description

Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.

Affected products

Vendor Intel Product Intel(R) MAX(R) 10 FPGA Default
n/a
- Version
  All versions
  Status
  affected
  Constraints
  -
- Version
  See advisory https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html
  Status
  affected
  Constraints
  -

Default status is the baseline for the product, each version can override it (e.g. patched versions marked unaffected).

Vendor

Product

Default status

Versions

Intel

Intel(R) MAX(R) 10 FPGA

n/a

Version	Status	Constraints
All versions	affected	-
See advisory https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html	affected	-

Remediation

No remediation recorded yet.

Weaknesses (0)

No CWE recorded.

References (2)

https://euvd.enisa.europa.eu/vulnerability/EUVD-2020-2072
Advisory
https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html
x_refsource_CONFIRMVendor Advisory

Link	Providers	Tags
https://euvd.enisa.europa.eu/vulnerability/EUVD-2020-2072		Advisory
https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html		x_refsource_CONFIRMVendor Advisory